The demand for ever higher circuit board density has resulted in small size semiconductor devices having a low profile. Board space considerations have traditionally been viewed from a two dimensional perspective, and the motivation for thin packaging has been a secondary issue. However, with the electronic industry is looking at thin packaging to address density issues associated with products like memory cards, smart cards, and emulator cards, package thickness is now a critical factor.
EPROM packaging is more expensive than conventional molded plastic packages due to the need of a glass window to expose the memory chip to ultra violet light to erase the data stored in the memory cells. The standard package for such devices is an expensive ceramic cavity package with a light transmissive glass lid over the top of the package and above the memory device.
Prior art packages which include conventional packaging such as National Semiconductors TapePak.TM., Tape Automated Bonding (TAB), Dual In-line Plastic (DIP) packages, and Small Outline Packages (SOPs) are not used since these plastic encapsulated packages do not provide the ultra violet transmissive windows. Conventional prior art packages use wire bonds to interconnect the chip to a leadframe which is an integral part of a ceramic cavity package. A quartz lid is applied over the opening to the cavity after wire bonding. The chip is sealed inside the cavity to make a hermetic package. The cost of this packaging technique is very expensive in both material and assembly labor. Prior art semiconductor devices are packaged prior to testing and burn-in such that if the device tests to be a faulty device, then the costs of manufacturing the entire device is lost. TAB packaging uses a liquid plastic to encapsulate the semiconductor chip resulting in much simplified process steps and material cost savings.